1. Field of the Invention
This invention relates to field-effect transistors (FETs) and MOS (Metal Oxide Semiconductor) devices in which the gate consists of a layer or layer(s) of cladded nanoparticles or cladded quantum dots. Depending on the configuration of the gate layers consisting of cladded quantum dots and insulating layers, the structure behaves as fast access nonvolatile memory structure or as a FET exhibiting multiple states (such as three-state) in its drain current-gate voltage characteristics (also known as transfer characteristics). The three-state FETs can be used for various circuit applications including multi-valued logic gates with reduced device count for a given functionality or in the implementation of analog circuits. Another innovative feature is the use of an asymmetric coupled quantum well transport channel that enhances the retention time in a nonvolatile memory by increasing the ‘effective’ separation between channel charge (located in the lower quantum well) and the quantum dots in various layers of the floating gate storing a multiplicity of bits.
2. Brief Description of Prior Art
Nonvolatile memories are used to store information in microchips. Floating trap memory [realized as SONOS (Si-Oxide-Nitride-Oxide-Si) structures] and floating gate memories are two generally used configurations [Brown and Brewer (1998) and Cappelletti et al. (1999)]. Another important category is nonvolatile random access memories (NVRAMs) which are generally realized as magnetic RAMs (MRAMs), ferroelectric devices, SRAMs (static RAMs) with nonvolatile devices connected in parallel, and more recently carbon nanotube based memories (here the state of carbon nanotube depends on the gate operating conditions). These memory devices are continually being scaled down to smaller sizes (such as sub 100 nm) with fast access time and smaller operating voltages. FIGS. 1 and 2 show two commonly used nonvolatile memory structures. There are many variations.
Nonvolatile floating gate quantum dot memories (QDMs), shown in. FIG. 3a, represent another class of nonvolatile memories that are reported in the literature [Tiwari et al. 1995, 1996]. In quantum dot gate nonvolatile memories, the charge is discretely localized on the quantum dots, The charge distribution on the floating quantum dots is not continuous like conventional devices, and is determined by the tunneling of hot carriers at the drain end or from the channel. FIG. 3b shows a strained layer Si transport channel which is realized on SiGe layer [Hasannen et al, 2004]. This structure could also be realized in silicon-on-insulator (SOI) configuration. Ostraat et al. [2001] have reported floating gate memory structures using Si nanocrystals. They have summarized the advantages of nanocrystal based charge storage including: 1) reduced punch-through by reducing drain to floating gate coupling, 2) reduction in stress induced leakage currents, and 3) potentially enhanced retention times.
The QDMs have advantages of high-speed write/erase, scalability to sub-22 nm, and lower operating voltage over the conventional floating gate memories and floating trap or SONOS (Si-Oxide-Nitride-Oxide-Si) memories. However, the conventional QD based nonvolatile memory suffers from small retention time and fluctuations of electrical characteristics. In the current quantum dot gate device processing there is little control over the location of Si nanoparticles in the gate, their sizes, as well as the separation between them. Invariably, these dots are not cladded. Some reports outline forming cladding is in the literature after the dots are created. Here, they again suffer from the dot size variation problem.
What is needed is a nonvolatile memory device, which solves the above problems and which exhibits fast ‘write’ and ‘access time’ with desirable long ‘retention time’ for various applications. This is achieved, as described in this patent, by using cladded quantum dots (with appropriate core and cladding thicknesses) that are assembled or deposited on the transport channel of a FET forming the floating gate. In one embodiment, we describe the use of monodispersed SiOx cladded Si quantum dots constituting the floating gate layer. The cladding maintains a sufficient separation between Si nanodots, and between dots, transport channel and the control gate; thereby controlling the inter-dot tunneling and also improving the ‘write and read’ and the retention time characteristics. Self-assembled SiOx—Si quantum dots also provide high dot density resulting in improved threshold shift and dual-bit cell ‘read’. Deposition of mono-dispersed SiOx—Si dots having dot size uniformity using site-specific self-assembly technique (which enables smaller deviation in size and dot placement) ensures smaller deviation in the device characteristics.
Another innovation pertains to the design of transport channel in which carriers flow between the source and drain. The transport channel is comprised of a coupled well structure, which has more than one wells and appropriate number of barrier layers forming the basic FET structure. An asymmetric coupled quantum well transport channel is formed when the two quantum wells are of different thicknesses and consist of a barrier layer between them. This structure enhances the retention time in a nonvolatile memory by increasing the ‘effective’ separation between channel charge (located in the lower well) and the nanodots located in the floating gate without significantly increasing the ‘program’ voltage for a given tunnel oxide thickness. In the case of FETs, coupled well are known to improve the high frequency operation [Jain and Heller (2002) and Heller et al. (1999)].
The usage of asymmetric coupled well transport channel structure along with cladded SiOx—Si dot gate solves various challenging problems (mentioned above for QDM devices) particularly, in scaled-down FET-based memory structures. It provides additional control to limit the gate leakage current. In the case of nonvolatile memory, it enhances charge retention.
The three-state FETs which also use cladded quantum dots in the gate layers is a novel device described in this document. As a background of bistable devices, Kouklin et al. [2000] have reported bistable devices using self-assembled 10 nm CdS quantum dots using nanoporous anodic alumite films as the template. The three-state FET devices presented here are quite different from these conventional quantum dot structures reported in the literature. They are different from nonvolatile memory in a subtle way which is described in later sections of this document.